1. Field of the Invention
This invention relates to the fabrication of integration circuit wafers, and more particularly to an apparatus and method for fabricating p-channel and n-channel selectively doped heterostructure transistors on the same wafer.
2. Description of the Related Art
Large scale integration (LSI) and very large scale integration (VLSI) memory logic technology typically requires a complementary integrated circuit (IC) which combines intrinsic high switching speed, large noise margins and very low stand-by power dissipation. An answer to this requirement has been the development of the selectively doped heterostructure transistor (SDHT), also known as the high electron mobility transistor (HEMT) or the modulation doped field effect transistor (MODFET). The SDHT is considered to be the fastest switching semiconductor device presently known. It obtains its speed from the presence of a heterojunction, usually between GaAs and Al.sub.x Ga.sub.1-x As. Furthermore, GaAs has a much higher electron mobility than does Si, making GaAs FETs high interest candidates for high-speed integrated circuits.
An important aspect of SDHTs is that the carrier is a quasi two-dimensional electron gas (2DEG). The electron gas is considered quasi two-dimensional because its depth is quite small compared to its width and length. A 2DEG is produced and confined to the side of the heterojunction interface containing the smaller bandgap material; in a GaAs-Al.sub.x Ga.sub.1-x As junction, the 2DEG is confined to the GaAs interface. Therefore, the GaAs layer in a MODFET is equivalent to the Si substrate of a MOSFET and the Al.sub.x Ga.sub.1-x As layer is comparable to the SiO.sub.2 layer.
While n-channel GaAs FETs have had impressive speed performance, complementary GaAs circuits employing both p-channel and n-channel transistors, particularly complementary p- and n-MODFETs, are much preferable in terms of power dissipation, noise margin and overall circuit integration level.
Numerous unsuccessful attempts have been made to obtain complementary n- and p-MODFETs on the same wafer. Because of the difficulty in achieving such a device, resort has been had to complementary p- and n-channel devices built which mimic a complementary MODFET pair, with varying results. In one such complementary transistor arrangement, a device employed a complementary p-MODFET and an n-channel heterostructure barrier MESFET, not a SDHT, on the same wafer using selective etching. See R. A. Kiehl and A. C. Gossard, "Complementary p-MODFET and n-HB MESFET (Al,Ga)As Transistors," IEEE Electron Device Letters, Volume EDL-5, No. 12, December 1984.
FIG. 1 depicts this n-channel HB-MESFET and p-MODFET device. The transistors shown were fabricated on a molecular beam epitaxially grown wafer consisting of the following successive layers for the p-channel MESFET; a Cr-doped GaAs substrate 2, an undoped intrinsic GaAs layer 4, and a Be-doped p-AlGaAs layer 6; for the n-channel HB-MESFET; a Cr-doped GaAs substrate 2, an undoped intrinsic GaAs layer 4, a Be-doped p-AlGaAs layer 6, and a Si-doped n-GaAs layer 8. A window 10 was etched into the intrinsic GaAs layer 4 in regions where the p-MODFETs were to be fabricated, thereby defining the mesas for the two transistors. An AuBe-based p-type metallization was deposited as a drain ohmic contact 12 and a source ohmic contact 14 on p-AlGaAs layer 6 of the p-channel MODFET. This was followed by the deposition of an AuGe-based n-type metallization as drain ohmic contact 16 and source ohmic contact 18 onto the Si-doped n-GaAs layer 8 of the n-channel HB-MESFET. Next, gate contacts 20,22 were deposited on areas which were chemically recessed into n-GaAs layer 8 and p-AlGaAs layer 6, respectively. These gates were typically formed by Ti/Au metallization.
This arrangement yields a complex and undesirable non-planar wafer surface. Not only is the fabrication of such a device quite complex and difficult, with most of its layers alternating between transistors as the device is being fabricated, but the MESFET has a much slower electron mobility. In a MESFET, the carriers must travel in the doped channel and encounter large scale scattering, resulting in slower velocities and slower switching responses than in a MODFET. In a MODFET, the carriers (2DEG) travel in the intrinsic small band material of the heterojunction. Since there are virtually no impurities to scatter the carriers, MODFETs have significantly better response and switching times, brought about by the increased carrier mobility. Therefore, a p-channel MODFET integrated with an n-channel MODFET would be highly desirable.
In another prior complementary transistor device, complementary HIGFETs were employed in an attempt to yield results comparable to the desired complementary p-MODFET and n-MODFET integrated device. See, W. C. Cirillo, Jr., et al., "Complementary Heterostructure Insulated Gate Field Effect Transistors (HIGFETs)", IEEE publication IEDM 85, pages 317-320. HIGFETs are also known as metal-insulator-semiconductor heterostructure FETs or MISFETs. As shown in FIG. 2, the device employed two HIGFETs which were epitaxially grown on the same semi-insulating GaAs substrate 24. Onto this substrate was grown an undoped GaAs buffer layer 25 with an undoped AlGaAs insulating layer 26. WSi Schottky gates 28 and 30 were deposited onto the n-channel and p-channel HIGFETs, respectively. The source and drain regions of both the n- and p-channel HIGFETs were then formed by ion implantation of Si and Mg, respectively. The n.sup.+ implanted regions 32, 34 and the p.sup.+ implanted regions 36, 38 were activated by annealing. Ohmic source contact 40 and ohmic drain contact 42 were deposited onto the n.sup.+ implanted regions 32, 34, respectively, by an AuGeNi-based metallization. Similarly, ohmic source contact 44 and ohmic drain contact 46 were deposited onto the p.sup.+ implanted regions 36, 38, respectively, by an AuZn-based metallization. 2DEG 48 was formed between AlGaAs insulating layer 26 and GaAs buffer layer 25, extending between n.sup.+ implant regions 32 and 34. Likewise, 2DHG 50 was formed between insulating layer 26 and buffer layer 25, extending instead between p.sup.+ implant regions 36 and 38. N- and p-HIGFET isolation was achieved using a selective implant, such as oxygen, to introduce traps and increase resistance between transistors.
Although fabrication of the FIG. 2 HIGFETs is much easier than the FIG. 1 structure, HIGFETs have several limiting characteristics. First, the threshold control is not adjustable; the threshold of both n- and p-channel devices voltage is fixed to an undesirable value. The threshold voltage, V.sub.t, is determined by the Schottky barrier height of the heterostructure as well as the band offsets in the conduction and valence bands. For example, the typical refractory metal (e.g. tungsten) gate HIGFET has a threshold voltage of +0.8 volts, too high for typical integrated circuits because 0.8 volts is needed to turn the device on.
Second, since there is no charge available in an intrinsic material, one must bias the metal gate to shift the energy levels to obtain and confine the 2DEG and the 2DHG (two-dimensional hole gas). The most desirable arrangement for complementary devices is to not only have an adjustable threshold voltage V.sub.t, but also to have the device produce a large enough current flow at room temperature (300.degree. K.) with a gate voltage at 0.2 or 0.3 volts. At 300.degree. K. the HIGFET output current is so negligible one cannot measure the I-V characteristics of an n- or p-channel HIGFET, so the device must be cooled, typically down to 77.degree. K., to be usable. Even at 77.degree. K., when the gate voltage V.sub.g is zero, there is no current flowing for the n-HIGFET; an undesirable 2 volt positive V.sub.g must be applied to receive a 5 mA drain current. With the p-HIGFET, when V.sub.g is zero there is no current flowing either; an undesirable negative 1.8 volts V.sub.g is necessary to obtain approximately a 1.2 mA drain current.
Additionally, the threshold voltage of n- and p-HIGFETs is non-uniform due to large subthreshold current leakage. Furthermore, the I.sub.ds -V.sub.ds curve of the p-HIGFET becomes quite distorted at low drain-to-source voltages due to the large contact resistances.